1. Field of the Invention
The present invention relates to a data processor, more particularly to a data processor being provided with instructions capable of inserting and extracting data to and from optional bit area of a register, and to a control circuit therefor.
2. Description of the Related Art
At graphic processings in a printer or the like, it is often required to operate pixel data one by one byte.
Specifically, such operations as inserting pixel data at an optional byte position of a register and extracting pixel data from an optional byte position of the register are frequently carried out.
There are instructions to support such operations, for example, such as the EXBYTE, EXHW, EXHWS, INBYTE and INHW instructions of 32-bit microprocessor Am29000 series of AMD (Advanced Micro Devices Inc.).
FIG. 1 schematically shows formats of the instructions provided for the Am29000 series described above.
Instruction code of every instruction has a fixed length of 32 bits (4 bytes) with the head byte being the operation code.
The operation code is set to "0000101M" for the EXBYTE instruction 301, "0111110M" for the EXHW instruction 302, "01111110" for the EXHWS instruction 303, "0000110M" for the INBYTE instruction 304, and "0111100M" for the INHW instruction 305.
Only the EXHWS instruction has two operands, and all other instructions each have three operands. The second byte from the head byte of each format is used for specifying the destination, the third byte for source A and the last byte for source B (irrelevant to the EXHWS instruction wherein the last byte is reserved).
Any one of registers from 32 registers, number 0 through number 31, of a register file is specified as the source A operand and the destination operand.
Any one of registers from the registers, number 0 through number 31, or an 8-bit value is specified as the source B operand.
Operation of each instruction is illustrated in the schematic diagrams of FIG. 2 through FIG.
In FIG. 2 through FIG. 8, A1 through A4 represent the values of first byte through fourth byte of the source A operand, and B1 through B4 represent the values of first byte through fourth byte of the source B operand, respectively.
As shown in FIG. 2, the EXBYTE instruction stores the source B operand, with data "B4" at the lowest byte thereof being replaced by data "A2" located at a specified byte position of the source A operand, in the destination register.
As shown in FIG. 3, the EXHW instruction is a variation of the EXBYTE instruction with the size of data to be replaced by the instruction being changed from one byte to two bytes.
As shown in FIG. 4, the EXHWS instruction applies sign extension to 2-byte data located at a specified position of the source A operand into 32 bits, and stores it in the destination register.
As shown in FIG. 5, the INBYTE instruction stores the source A operand, with data "A2" located at a specified byte position thereof being replaced by data "B4" located at the lowest byte position of the source B operand, in the destination register.
As shown in FIG. 6, the INHW instruction is a variation of the INBYTE instruction with the size of data to be replaced by the instruction being changed from one byte to two bytes.
Position of the data to be operated in the source A operand is specified by a byte position field of an ALU status register.
Because the "instructions which insert and extract data to and from optional byte position of a register" provided on the data processor of the prior art specify the byte position with the value of a control register, it is necessary to set the byte position to be processed onto the control register before executing the instruction. This requires one or more additional instruction to be executed in addition to the intrinsic instructions for the intended operations, leading to increasing processing time and instruction code size.
Also because these instructions are capable of specifying only registers as data to be inserted and operands to be extracted, in the case where the data are stored in a memory, transferring the data between the register and the memory in advance is required. This makes it necessary to execute one or more extra instructions in addition to the intrinsic instruction of the operation, thus increasing the processing time and instruction code size similarly to the problem described above.